tsmc stelt duurste asml-machines uit tot 2029
Taipeh, zaterdag, 25 april 2026.
TSMC, de grootste klant van ASML, schort de aanschaf van de nieuwste high-NA EUV-machines op tot 2029. Ondanks de druk om de meest geavanceerde chips te produceren, kiest het bedrijf bewust voor kostencontrole. De machine zelf kost ruim 350 miljoen euro. In plaats daarvan haalt TSMC extra prestaties uit bestaande technologie. Dat verrast de markt en werpt vragen op over de snelheid van technologische vooruitgang. Volgens topman Kevin Zhang zien ze nu geen meetbaar voordeel. ASML voelt de impact direct via lagere omzetverwachtingen.
tsmc postpones high-na euv adoption despite roadmap advances
Taiwan Semiconductor Manufacturing Company (TSMC) has confirmed it will delay acquiring ASML’s newest high-NA extreme ultraviolet (EUV) lithography systems until 2029 [1]. This strategic pause applies even as TSMC maps out advanced production nodes like A13 and A12 for 2029 [2]. The decision stems from a combination of escalating equipment costs and confidence in optimizing existing EUV infrastructure [3]. High-NA EUV machines, critical for sub-2nm chip fabrication, carry a price tag exceeding €350 million each [4]. By extending the lifecycle of current EUV tools, TSMC aims to control capital expenditure while sustaining technological progress [5].
cost concerns shape equipment strategy
The staggering expense of high-NA EUV systems is central to TSMC’s postponement [4]. At over €350 million per unit, these machines represent a significant financial commitment amid already soaring fab construction costs, which now range between $20 billion and $30 billion [3]. TSMC leadership, including Deputy Co-Chief Operating Officer Kevin Zhang, emphasizes that current EUV technology can still achieve necessary scaling improvements without immediate reliance on high-NA tools [5]. Zhang stated the company will act only when high-NA delivers “meaningful, measurable benefit,” indicating today’s enhancements render it unnecessary for upcoming nodes [1][5]. This fiscal discipline supports TSMC’s target of sustained gross margins above 56 percent [3].
existing technology meets near-term demands
TSMC asserts its present EUV capabilities suffice for rolling out next-generation semiconductors through 2029 [1]. The A13 process, described as a 1.3nm node, achieves approximately 6% better area efficiency compared to A14 using refined versions of current technology [2][5]. Similarly, the A12 node, featuring innovations like backside power delivery via Super Power Rail, does not necessitate high-NA EUV [2]. Engineers continue refining techniques such as double patterning and computational lithography to extract additional performance [5]. This capability allows TSMC to defer multi-billion-dollar upgrades while fulfilling demand from major clients in artificial intelligence and high-performance computing sectors [3].
impact on asml and market dynamics
As TSMC is ASML’s largest customer, the delayed orders pose a direct commercial challenge [3]. Investor sentiment reacted swiftly, with ASML’s U.S.-listed shares dropping up to 5.5% following the announcement [3]. Market expectations previously anticipated a faster ramp-up of high-NA EUV deployment around 2027–2028 [3]. While TSMC has acquired some high-NA units, they remain confined to R&D purposes rather than volume manufacturing [3]. Other manufacturers like Intel plan earlier integration, but TSMC’s decisions often set industry benchmarks [1]. Consequently, ASML’s path toward its long-term €60 billion revenue ambition hinges partly on overcoming such adoption hesitations [3].
broader implications for semiconductor advancement
This development underscores growing economic pressures in cutting-edge chip manufacturing [3]. Shrinking transistor sizes now require exponentially larger investments, prompting companies to scrutinize returns more closely [3]. TSMC’s ability to postpone high-NA adoption suggests innovation isn’t solely dependent on newer hardware—software, materials science, and process engineering play vital roles [5]. However, there remains concern about eventual physical limitations of current EUV systems, beyond which high-NA becomes indispensable [1]. Industry observers note that while delays ease short-term budgets, prolonged deferral could eventually affect global competitiveness in semiconductor leadership [alert! ‘long-term effects uncertain’].